LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY jishi IS
PORT
(	--start:	IN STD_LOGIC;
	clk_in:IN STD_LOGIC;
	sec_outl:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
	sec_outh:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
	sec_decimalh,sec_decimall:OUT INTEGER RANGE 0 TO 9;
	state_in:IN INTEGER RANGE 0 TO 4;
	state_out:OUT STD_LOGIC
	--counttest:OUT INTEGER RANGE 99 DOWNTO 0--for debug
);
END jishi;

ARCHITECTURE behave of jishi IS
	SIGNAL high_temp:STD_LOGIC_VECTOR(3 DOWNTO 0);
	SIGNAL low_temp:STD_LOGIC_VECTOR(3 DOWNTO 0);
	SIGNAL count:INTEGER RANGE 99 DOWNTO 0;
BEGIN
	p1:PROCESS(clk_in,state_in)
	BEGIN 
		--IF(state_in=0 OR start='1') THEN
		IF(state_in=0 ) THEN
			count<=99;
		ELSIF(clk_in'EVENT AND clk_in='1') THEN
			IF count=0 THEN
				count<=0;
				state_out<='0';--output the state of counter
					
			ELSE 
					count<=count-1;
					state_out<='1';
			END IF;
		END IF;
		
			
		
	END PROCESS p1;
	
	p2:PROCESS(count)
	BEGIN 
		low_temp<=CONV_STD_LOGIC_VECTOR(count rem 10,4);
		high_temp<=CONV_STD_LOGIC_VECTOR(count/10 rem 10,4);
		sec_decimalh<=count/10 rem 10;
		sec_decimall<=count rem 10;
	END PROCESS p2;
	
	sec_outl<=low_temp;
	sec_outh<=high_temp;
	--counttest<=count;
END  behave;
		